Designing Performance Enhanced Digital Signal Processors Using Loop Transformations

Digital Signal Processors (DSPs) are employed in all fields of multimedia applications such as speech, audio, modem, video, or graphics. Often, they are embedded into multimedia systems as a System on Chip (SoC) component. Although DSPs could still be modified in the SoC domain, they are mainly employed as fixed DSP cores. Possible adaptations to the embedding system are not carried out. Thus, if a multimedia system requires more hardware performance, either additional DSP cores or dedicated ASICs have to be added, which limits flexibility. The main reason is that today’s DSP cores are not designed for extensions. Thus, our work is targeted to design a family of scalable DSP architectures. One class of this DSP family comprises an extendable architecture with standard DSP components such as one MAC unit and one dual port memory. In this paper we present methods to extend this DSP core automatically without changing the core itself. With these methods, the DSP architecture can be reconfigured and, thus, easily adapted to different system requirements.